Back to where I was

It took a while, but I’ve managed to get the root<->G2 transactions working with what should be correct clock domain crossing (CDC). Now I’m back to where I was about a year ago. Most of the assumptions made with the previous method were relying heavily on the G2 clock lining up with the board’s system clock. Naively, an attempt was made to detect when the G2 clock was toggling to allow for the data to be transferred. This would work most of the time, but it would fail every few minutes or a few times in a short period of time.

After a long-form test of around nine hours, the new method with CDC held up without causing any issues. The most difficult part was accounting for DMA transfers. Mainly due to the delay in the data from the target or host being offset by a few clocks while the asynchronous FIFO was getting ready. It took about a week, but the DMA transfers are working as expected. I’ve yet to bring interrupts back, which will be the next thing after data from the TF card is once again ensconced within the DMA memory.

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Networking progress

During all of this, I couldn’t help myself but attempt to send some data from the Ethernet PHY. It half-works. There’s no flow control, so I’m only able to reliably send a few packets a second and the receive interface is non-existent. I have a few captures from a Fluke LANMeter, which is a tool that proved invaluable for this:

The following two images display the FCS errors encountered on station 00:11:22:33:44:55. I’ve since adopted 00:D0:F1:FF:xx:xx as the test MACs.

This is another view with an overview of the frames going over the network.

These images show the NIC test in action. There are problems with the auto-negotiation. In this case, a crossover cable was used.

If all goes well, I’d like to have some basic functionality of the RTL8139 completed by the end of the year.